Prior art phased lock loops (PLLs) use measurement of the phase difference between a reference signal and the feedback signal, after frequency division, to adjust the frequency of a digitally controlled oscillator that generates the feedback signal. A frequency division can be employed in the reference signal and/or the feedback signal before prior to phase error measurement.
A digital phase locked loop (DPLL) in general comprises a phase comparator, a loop filter, a digital controlled oscillator, and a feedback path. The feedback signal is compared with a reference signal to generate an error signal. The loop filter filters the error signal to generate the control signal for the digital controlled oscillator. In this way the output of the phase locked loop is locked to the reference signal. The convergence time is the time it takes for the output to lock on to the reference signal and is proportional to the filter bandwidth. A low filter bandwidth is desirable to reduce jitter but this implies a long convergence time.
In one type of DPLL, known as a type II PLL, the loop filter is of second order. The loop filter has two parts, known as the proportional or P-part, and integral I-part, which generate corresponding components of the DCO frequency control signal. The I-part accumulates the phase errors into a frequency offset, which is added to the instantaneous phase from the P-part in each cycle. The convergence time is normally dominated by the P-part. However, when the frequency is in lock with the reference signal and the I-part has a small frequency offset, the residual phase convergence time is governed by the small error from the I-part. Under these circumstances the phase error can be corrected extremely slowly, especially when the loop bandwidth is low.
A typical type II DPLL 10, shown in FIG. 1, comprises a phase comparator 12 to measure phase error, a loop filter 14, and a digital controlled oscillator (DCO) 16. The phase comparator 12 compares the phase of a reference clock Φref (or a reference clock divided by 1/M in frequency divider 18) and the output of the local DCO 16 or some derivative thereof, for example, a fraction thereof (through frequency divider 20), potentially with some preset offset, with the phase error Φerr being the output of phase comparator 12. It will be understood that the DPLL 10 operates under the control of a system clock (not shown).
A typical loop filter 14 includes a proportional (P) component 22 and an integral (I) component 24, as shown in FIG. 2. In the proportional (P) component 22 of loop filter 14, multiplier 26 multiplies the output Φerr of a phase comparator used as the phase error measurement element 12 by the scaling factor KP. The output of multiplier 26 is provided to the integral (I) component 24 including multiplier 28 having the integral factor KI as an input. An integrator consisting of adder 30 and memory 32 with a unit delay forms part of a delayed feedback loop. The multiplier 26 produces a phase compensation component dfp and the multiplier 28 and integrator (adder 30 and memory 32) produce an integral component dfi, representing a frequency offset relative to the frequency of the reference clock Φref. The components dfp and dfi are further summed in adder 34 to produce a control signal df which is arranged to set the frequency of the DCO 16 of FIG. 1 so that it becomes locked to the reference clock Φref.
The memory 32 stores the value of the frequency component dfi for one cycle so that the current inputs to the adder 30 are (previous cycle dfi)+KI*dfp (current cycle). Consequently the DCO control signal df at the output of the adder 34 is given by df=dfp (current cycle)+dfi (previous cycle)+KI*dfP (current cycle).
The loop bandwidth is generally set by user and is determined by the scaling factor KP, which is typically set to be: KP=2πf/fsys, where f is the loop bandwidth and fsys is the system clock frequency for the DPLL 10. The multiplier 26 will give an instantaneous PLL update value dfp, since there is no memory component. The integral factor KI, which is input to the multiplier 28, maintains the filter integral part at a very low rate in relation to the instantaneous PLL update value dfp and in general: KI=KP/D, where D>>1 is a damping factor.
When phase difference is the only variable considered when correcting the frequency of the DCO, the locking range of the PLL is limited by the loop bandwidth. To increase the locking range the loop gain has to be increased which in turn increases the frequency noise in the output.
Therefore, there is a need for a new way to control a PLL which is not associated with these disadvantages.